1. Field of the Invention
The present invention relates to package structures and fabrication methods thereof, and more particularly, to a carrier-free package structure and a fabrication method thereof.
2. Description of Related Art
Along with the rapid development of electronic industries, many high-end electronic products are developed toward the trend of high integration. Accordingly, various chip packaging technologies are developed and chip packaging sizes are continuously reduced to meet the miniaturization requirement of semiconductor packages.
FIGS. 1A to 1F are schematic cross-sectional views showing a method for fabricating a package structure according to the prior art.
Referring to FIG. 1A, a circuit layer 11 is formed on a carrier 10.
Then, referring to FIG. 1B, a plurality of conductive posts 13 are formed on a portion of the circuit layer 11.
Thereafter, referring to FIG. 1C, a dielectric body 12 is formed on the carrier 10 to embed the conductive posts 13 and the circuit layer 11 therein. The dielectric body 12 has a first surface 12a formed on the carrier 10 and a second surface 12b opposite to the first surface 12a. 
Referring to FIG. 1D, the carrier 10 is partially removed. As such, the remaining portion of the carrier 10 forms a carrier 10′. Further, a semiconductor element 40 is disposed on the first surface 12a of the dielectric body 12.
Referring to FIGS. 1E and 1F, a mold 90 is disposed on the carrier 10′ and thus a receiving space 900 is formed between the first surface 12a of the dielectric body 12 and the mold 90. Then, an encapsulant 42 is injected into the receiving space 900. As such, a package structure 1 is formed, as shown in FIG. 1F.
In the above-described method, the carrier 10′ supports the overall structure so as to prevent warping of the package structure during high temperature processes.
However, limited by current processing methods, the carrier 10′, such as a steel board, has a minimum thickness of 200 μm. As such, even if the mold cavity of the mold 90 is flush with the carrier 10′, as shown in FIG. 1E′, the thickness h1 of the encapsulant 42 is still limited by the minimum thickness of the carrier 10′ of 200 μm. Therefore, the thickness of the overall package structure is difficult to be reduced and consequently the package structure cannot meet the miniaturization requirement of electronic products.
Therefore, there is a need to provide a package structure and a fabrication method thereof so as to overcome the above-described drawbacks.